Role Title: ASIC/RTL Design Engineer - Senior
Location: San Jose, CA (4 days a week in office, Friday optional)
Duration: 12+ months contract
KEY RESPONSIBILITIES:
- Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
- Collaborate with architecture and hardware teams to understand the requirements.
- Work with verification and physical design teams to achieve high quality design and successful tape out.
- Design and implement logic functions that enable efficient test and debug.
- Participate in silicon bring-up for features owned.
- Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
- Implement automation to increase design team efficiency.
PREFERRED EXPERIENCE:
- Must have proven track record of ASIC design on several production tape-outs.
- Experience in Designing RTL block for an SOC.
- Experience in integrating ASIC IP into an SOC.
- Experience with Arm architecture and APB, AXI, CHI protocols.
- Experience with synthesis, static timing analysis & optimizations.
- Experience with design involving Interconnects.
- Experience writing timing constraints and exceptions.
- Experience with automation using scripting techniques such as PERL, Python or Tcl
- Ability to develop clear and concise engineering documentation.
- Experience in Power-saving techniques.
- Ability to organize and present complex technical information.
- Strong verbal and written communication skills
Job Type: Contract
Pay: $150,000.00 - $200,000.00 per year
Benefits:
- 401(k)
- 401(k) matching
- Dental insurance
- Health insurance
- Life insurance
- Paid time off
- Vision insurance
Schedule:
Ability to Commute:
- San Jose, CA 95110 (Preferred)
Ability to Relocate:
- San Jose, CA 95110: Relocate before starting work (Required)
Work Location: In person