We’re Hiring!
Our key client in clinical robotics is looking for additional members for their team. We have a Design Verification Engineer on the team.
Pay Rate: $100.00-$130.00/hour on W2
Work Type: Hybrid - Sunnyvale, CA 94086
Duration: 6-month contract (with possible extension)
Key Responsibilities:
- Responsibilities include starting from test planning to closing verification using coverage metrics.
- Involves testbench development from scratch or modification to existing testbench infrastructure for verifying new features.
- Work closely with the design team to review specifications and architecture, extract features, and define a verification plan & coverage model.
- Directed/constrained random test generation, failure analysis, resolution, and coverage analysis.
- Debugging failures, bug tracking, and analyze and close coverage.
Qualifications:
- Advanced knowledge of HVL methodology (UVM).
- Expertise in HVL and HDL (SystemVerilog, Verilog).
- Experience defining coverage space and writing coverage models.
- Experience with SystemVerilog Assertion (SVA) is a plus.
- Team player with excellent communication skills and the desire to take on diverse challenges.
- Experience writing scripts in languages such as Perl/Python.
- Solid verification skills in problem-solving, constrained random testing, and debugging.
- Experience with Veloce or other HW accelerators and Formal is a plus.
Raise PBC is committed to a policy of nondiscrimination and equal opportunity for all employees and qualified applicants without regard to race, color, religious creed, national origin, ancestry, age, disability, genetics, gender identity, veterans' status, sexual orientation, or any other characteristic protected by law. Raise PBC is an equal-opportunity employer encouraging diversity in the workplace.\
#USVM
Job Type: Contract
Pay: $100.00 - $130.00 per hour
Benefits:
- Dental insurance
- Health insurance
- Vision insurance
Schedule:
Work Location: In person